1. Field of the Invention
The present invention generally relates to a method for manufacturing solid-state devices and more particularly to method of using alignment marks on one side of a chip to determine locations of pads on the other side of the chip and to align the chip pads with substrate pads.
2. Description of the Related Art
Chip attachment technologies such as solder reflow, thermo-compression, and conductive adhesives are becoming mainstream processes for chip or integrated circuit device attachment. The advantages of surface mounted chips and other devices are well known to those skilled in the art. The most demanding aspect of chip/substrate assembly is generally regarded to be chip placement relative to the supporting substrate or board.
It is difficult to place chips, such as flip chips and other surface mounted devices and packages, accurately since the signal and attachment pads are between the carrier package (or circuit board) and the chip/package during placement. In other words, the connection pads on the chip and the connection pads on the substrate are out of view during the alignment and attachment process.
Conventional alignment techniques include acquiring the chip I/O (input/output) side pattern and the substrate I/O pattern; superimposing the I/O patterns; centering and rotating the chip/substrate to best align the I/O patterns; placing the chip on the substrate; and in certain instances, verifying the connections between the chip and the substrate by electrically testing the connections and/or observing the relatively irregular chip edge. Superimposing the substrate I/O pattern and chip I/O pattern is generally performed using prisms, up and downward observation optics, or other similar well known techniques/devices.
Such conventional techniques and devices are expensive and difficult to use from both hardware and control logic standpoints. Further, the placement and confident verification requires high degrees of mechanical, optical, and control system sophistication.
Chips and other solid state devices are constantly being redesigned to pack more function into smaller device sizes, often resulting in high value devices that need to be accurately mounted to be economically viable. Present industry trends are moving in the direction of smaller and smaller I/O contacts on ever smaller centers. These trends increase demands on flip-chip tooling, placement accuracy and verification capability. Furthermore, in the case of non-solder reflow type attachment processes (e.g., thermo-compression or conductive adhesive) placement accuracy of better than 90% is required.
Therefore, there is a need to increase the accuracy of aligning the chip with the substrate while decreasing the cost, complexity and equipment requirements. The invention, described in detail below, produces a less expensive, less equipment intensive and more accurate alignment of the chip and substrate than can be attained with conventional structures and methods.